/Users/ian/src/rp2040-psram/psram_spi.h

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/******************************************************************************
 
rp2040-psram
 
Copyright © 2023 Ian Scott
 
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the “Software”), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
 
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
 
THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
 
******************************************************************************/
 
#pragma once
 
#include "hardware/pio.h"
#include "hardware/gpio.h"
#include "hardware/timer.h"
#include "hardware/dma.h"
#if defined(PSRAM_MUTEX)
#include "pico/mutex.h"
#endif
#include "stdio.h"
 
#include "psram_spi.pio.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
typedef struct psram_spi_inst {
    PIO pio;
    uint sm;
#if defined(PSRAM_MUTEX)
    mutex_t mtx;
#endif
    int write_dma_chan;
    dma_channel_config write_dma_chan_config;
    int read_dma_chan;
    dma_channel_config read_dma_chan_config;
    int async_dma_chan;
    dma_channel_config async_dma_chan_config;
} psram_spi_inst_t;
 
static psram_spi_inst_t* async_spi_inst;
 
__force_inline extern void __time_critical_func(pio_spi_write_read_blocking)(
        psram_spi_inst_t* spi,
        const uint8_t* src, const size_t src_len,
        uint8_t* dst, const size_t dst_len
) {
    size_t tx_remain = src_len, rx_remain = dst_len;
 
#if defined(PSRAM_MUTEX)
    mutex_enter_blocking(&spi->mtx); 
#endif
    io_rw_8 *txfifo = (io_rw_8 *) &spi->pio->txf[spi->sm];
    while (tx_remain) {
        if (!pio_sm_is_tx_fifo_full(spi->pio, spi->sm)) {
            *txfifo = *src++;
            --tx_remain;
        }
    }
 
    io_rw_8 *rxfifo = (io_rw_8 *) &spi->pio->rxf[spi->sm];
    while (rx_remain) {
        if (!pio_sm_is_rx_fifo_empty(spi->pio, spi->sm)) {
            *dst++ = *rxfifo;
            --rx_remain;
        }
    }
 
#if defined(PSRAM_MUTEX)
    mutex_exit(&spi->mtx);
#endif
}
 
__force_inline extern void __time_critical_func(pio_spi_write_dma_blocking)(
        psram_spi_inst_t* spi,
        const uint8_t* src, const size_t src_len
) {
#ifdef PSRAM_MUTEX
    mutex_enter_blocking(&spi->mtx); 
#endif
    dma_channel_transfer_from_buffer_now(spi->write_dma_chan, src, src_len);
    dma_channel_wait_for_finish_blocking(spi->write_dma_chan);
#ifdef PSRAM_MUTEX
    mutex_exit(&spi->mtx);
#endif
}
 
__force_inline extern void __time_critical_func(pio_spi_write_read_dma_blocking)(
        psram_spi_inst_t* spi,
        const uint8_t* src, const size_t src_len,
        uint8_t* dst, const size_t dst_len
) {
#ifdef PSRAM_MUTEX
    mutex_enter_blocking(&spi->mtx); 
#endif
    dma_channel_transfer_from_buffer_now(spi->write_dma_chan, src, src_len);
    dma_channel_transfer_to_buffer_now(spi->read_dma_chan, dst, dst_len);
    dma_channel_wait_for_finish_blocking(spi->write_dma_chan);
    dma_channel_wait_for_finish_blocking(spi->read_dma_chan);
#ifdef PSRAM_MUTEX
    mutex_exit(&spi->mtx);
#endif
}
 
void __isr dma_complete_handler() {
    dma_hw->ints1 = 1u << async_spi_inst->async_dma_chan;
#ifdef PSRAM_MUTEX
    mutex_exit(&async_spi_inst->mtx);
#endif
}
 
__force_inline extern void __time_critical_func(pio_spi_write_async)(
        psram_spi_inst_t* spi,
        const uint8_t* src, const size_t src_len
) {
#ifdef PSRAM_MUTEX
    mutex_enter_blocking(&spi->mtx); 
#endif
 
    dma_channel_wait_for_finish_blocking(spi->async_dma_chan);
    async_spi_inst = spi;
 
    dma_channel_transfer_from_buffer_now(spi->async_dma_chan, src, src_len);
}
 
 
psram_spi_inst_t psram_spi_init(void) {
    uint spi_offset = pio_add_program(pio1, &spi_fudge_program);
    uint spi_sm = pio_claim_unused_sm(pio1, true);
    psram_spi_inst_t spi;
    spi.pio = pio1;
    spi.sm = spi_sm;
#if defined(PSRAM_MUTEX)
    mutex_init(&spi.mtx);
#endif
 
    gpio_set_drive_strength(PSRAM_PIN_CS, GPIO_DRIVE_STRENGTH_2MA);
    gpio_set_drive_strength(PSRAM_PIN_SCK, GPIO_DRIVE_STRENGTH_2MA);
    gpio_set_drive_strength(PSRAM_PIN_MOSI, GPIO_DRIVE_STRENGTH_2MA);
    gpio_set_slew_rate(PSRAM_PIN_CS, GPIO_SLEW_RATE_FAST);
    gpio_set_slew_rate(PSRAM_PIN_SCK, GPIO_SLEW_RATE_FAST);
    gpio_set_slew_rate(PSRAM_PIN_MOSI, GPIO_SLEW_RATE_FAST);
 
    pio_spi_fudge_cs_init(pio1, spi_sm, spi_offset, 8 /*n_bits*/, 1 /*clkdiv*/, PSRAM_PIN_CS, PSRAM_PIN_MOSI, PSRAM_PIN_MISO);
 
    // Write DMA channel setup
    spi.write_dma_chan = dma_claim_unused_channel(true);
    spi.write_dma_chan_config = dma_channel_get_default_config(spi.write_dma_chan);
    channel_config_set_transfer_data_size(&spi.write_dma_chan_config, DMA_SIZE_8);
    channel_config_set_read_increment(&spi.write_dma_chan_config, true);
    channel_config_set_write_increment(&spi.write_dma_chan_config, false);
    channel_config_set_dreq(&spi.write_dma_chan_config, pio_get_dreq(spi.pio, spi.sm, true));
    dma_channel_set_write_addr(spi.write_dma_chan, &spi.pio->txf[spi.sm], false);
    dma_channel_set_config(spi.write_dma_chan, &spi.write_dma_chan_config, false);
 
    // Read DMA channel setup
    spi.read_dma_chan = dma_claim_unused_channel(true);
    spi.read_dma_chan_config = dma_channel_get_default_config(spi.read_dma_chan);
    channel_config_set_transfer_data_size(&spi.read_dma_chan_config, DMA_SIZE_8);
    channel_config_set_read_increment(&spi.read_dma_chan_config, false);
    channel_config_set_write_increment(&spi.read_dma_chan_config, true);
    channel_config_set_dreq(&spi.read_dma_chan_config, pio_get_dreq(spi.pio, spi.sm, false));
    dma_channel_set_read_addr(spi.read_dma_chan, &spi.pio->rxf[spi.sm], false);
    dma_channel_set_config(spi.read_dma_chan, &spi.read_dma_chan_config, false);
 
    // Asynchronous DMA channel setup
    spi.async_dma_chan = dma_claim_unused_channel(true);
    spi.async_dma_chan_config = dma_channel_get_default_config(spi.async_dma_chan);
    channel_config_set_transfer_data_size(&spi.async_dma_chan_config, DMA_SIZE_8);
    channel_config_set_read_increment(&spi.async_dma_chan_config, true);
    channel_config_set_write_increment(&spi.async_dma_chan_config, false);
    channel_config_set_dreq(&spi.async_dma_chan_config, pio_get_dreq(spi.pio, spi.sm, true));
    dma_channel_set_write_addr(spi.async_dma_chan, &spi.pio->txf[spi.sm], false);
    dma_channel_set_config(spi.async_dma_chan, &spi.async_dma_chan_config, false);
    irq_set_exclusive_handler(DMA_IRQ_1, dma_complete_handler);
    dma_irqn_set_channel_enabled(1, spi.async_dma_chan, true);
    irq_set_enabled(DMA_IRQ_1, true);
 
    uint8_t psram_reset_en_cmd[] = {
        8,      // 8 bits to write
        0,      // 0 bits to read
        0x66u   // Reset enable command
    };
    pio_spi_write_read_dma_blocking(&spi, psram_reset_en_cmd, 3, 0, 0);
    busy_wait_us(50);
    uint8_t psram_reset_cmd[] = {
        8,      // 8 bits to write
        0,      // 0 bits to read
        0x99u   // Reset command
    };
    pio_spi_write_read_dma_blocking(&spi, psram_reset_cmd, 3, 0, 0);
    busy_wait_us(100);
    
    return spi;
};
 
 
static uint8_t write8_command[] = {
    40,         // 40 bits write
    0,          // 0 bits read
    0x02u,      // Write command
    0, 0, 0,    // Address
    0           // 8 bits data
};
__force_inline extern void psram_write8_async(psram_spi_inst_t* spi, uint32_t addr, uint8_t val) {
    write8_command[3] = addr >> 16;
    write8_command[4] = addr >> 8;
    write8_command[5] = addr;
    write8_command[6] = val;
 
    pio_spi_write_async(spi, write8_command, sizeof(write8_command));
};
 
 
__force_inline extern void psram_write8(psram_spi_inst_t* spi, uint32_t addr, uint8_t val) {
    write8_command[3] = addr >> 16;
    write8_command[4] = addr >> 8;
    write8_command[5] = addr;
    write8_command[6] = val;
 
    pio_spi_write_dma_blocking(spi, write8_command, sizeof(write8_command));
};
 
 
static uint8_t read8_command[] = {
    40,         // 40 bits write
    8,          // 8 bits read
    0x0bu,      // Fast read command
    0, 0, 0,    // Address
    0           // 8 delay cycles
};
__force_inline extern uint8_t psram_read8(psram_spi_inst_t* spi, uint32_t addr) {
    read8_command[3] = addr >> 16;
    read8_command[4] = addr >> 8;
    read8_command[5] = addr;
 
    uint8_t val; 
    pio_spi_write_read_dma_blocking(spi, read8_command, sizeof(read8_command), &val, 1);
    return val;
};
 
 
static uint8_t write16_command[] = {
    48,         // 48 bits write
    0,          // 0 bits read
    0x02u,      // Write command
    0, 0, 0,    // Address
    0, 0        // 16 bits data
};
__force_inline extern void psram_write16(psram_spi_inst_t* spi, uint32_t addr, uint16_t val) {
    write16_command[3] = addr >> 16;
    write16_command[4] = addr >> 8;
    write16_command[5] = addr;
    write16_command[6] = val;
    write16_command[7] = val >> 8;
 
    pio_spi_write_dma_blocking(spi, write16_command, sizeof(write16_command));
};
 
 
static uint8_t read16_command[] = {
    40,         // 40 bits write
    16,         // 16 bits read
    0x0bu,      // Fast read command
    0, 0, 0,    // Address
    0           // 8 delay cycles
};
__force_inline extern uint16_t psram_read16(psram_spi_inst_t* spi, uint32_t addr) {
    read16_command[3] = addr >> 16;
    read16_command[4] = addr >> 8;
    read16_command[5] = addr;
 
    uint16_t val; 
    pio_spi_write_read_dma_blocking(spi, read16_command, sizeof(read16_command), (unsigned char*)&val, 2);
    return val;
};
 
 
static uint8_t write32_command[] = {
    64,         // 64 bits write
    0,          // 0 bits read
    0x02u,      // Write command
    0, 0, 0,    // Address
    0, 0, 0, 0  // 32 bits data
};
__force_inline extern void psram_write32(psram_spi_inst_t* spi, uint32_t addr, uint32_t val) {
    // Break the address into three bytes and send read command
    write32_command[3] = addr >> 16;
    write32_command[4] = addr >> 8;
    write32_command[5] = addr;
    write32_command[6] = val;
    write32_command[7] = val >> 8;
    write32_command[8] = val >> 16;
    write32_command[9] = val >> 24;
 
    pio_spi_write_dma_blocking(spi, write32_command, sizeof(write32_command));
};
 
 
static uint8_t read32_command[] = {
    40,         // 40 bits write
    32,         // 32 bits read
    0x0bu,      // Fast read command
    0, 0, 0,    // Address
    0           // 8 delay cycles
};
__force_inline extern uint32_t psram_read32(psram_spi_inst_t* spi, uint32_t addr) {
    read32_command[3] = addr >> 16;
    read32_command[4] = addr >> 8;
    read32_command[5] = addr;
 
    uint32_t val;
    pio_spi_write_read_dma_blocking(spi, read32_command, sizeof(read32_command), (unsigned char*)&val, 4);
    return val;
};
 
 
static uint8_t write_command[] = {
    0,          // n bits write
    0,          // 0 bits read
    0x02u,      // Fast write command
    0, 0, 0     // Address
};
__force_inline extern void psram_write(psram_spi_inst_t* spi, const uint32_t addr, const uint8_t* src, const size_t count) {
    // Break the address into three bytes and send read command
    write_command[0] = (4 + count) * 8;
    write_command[3] = addr >> 16;
    write_command[4] = addr >> 8;
    write_command[5] = addr;
 
    pio_spi_write_dma_blocking(spi, write_command, sizeof(write_command));
    pio_spi_write_dma_blocking(spi, src, count);
};
 
 
static uint8_t read_command[] = {
    40,         // 40 bits write
    0,          // n bits read
    0x0bu,      // Fast read command
    0, 0, 0,    // Address
    0           // 8 delay cycles
};
__force_inline extern void psram_read(psram_spi_inst_t* spi, const uint32_t addr, uint8_t* dst, const size_t count) {
    read_command[1] = count * 8;
    read_command[3] = addr >> 16;
    read_command[4] = addr >> 8;
    read_command[5] = addr;
 
    pio_spi_write_read_dma_blocking(spi, read_command, sizeof(read_command), dst, count);
};
 
#ifdef __cplusplus
}
#endif